1. Field of the Invention
The present invention relates to a carrier reproduction circuit used in a receiver for receiving a signal transmitted via for example a satellite, such a receiver, and a loop filter circuit and an oscillator circuit used in the receiver etc.
2. Description of the Related Art
In May 1997, Japan""s Radio Regulatory Council gave its stamp of approval to a draft basic plan regarding promotion of broadcasting by satellites following the existing four systems (hereinafter, referred to as xe2x80x9cpost-BS-4 satellitesxe2x80x9d) so as to take over for example the standard television broadcasting of the stage of the third broadcasting satellite using the satellite use frequency. The plan called for (1) starting digital broadcasting by post-BS-4 satellites by the year 2000, (2) securing in the post-BS-4 satellites transitional channels for broadcasting of the same content as the existing four systems of broadcasting so as to take over the standard television broadcasting of the stage of the third broadcasting satellite, and (3) focusing on high definition television (HDTV) broadcasting other than (2).
Upon receipt of this report, the Japan Digital Broadcasting System Committee discussed technical conditions such as a transmission line encoding systems, multiplexing systems, a limited reception systems, and information source encoding systems assuming the requested conditions for satellite digital broadcasting based on proving tests. It issued a report concerning the technical conditions of the satellite digital broadcasting system in February 1998.
In this report, the Committee called for the adoption of trellis coded 8-phase shift keying (TC8PSK) with its high efficiency of frequency utilization among the phase shift keying (PSK) modulation systems suited for satellite transmission in the application of the specific transmission line encoding. Further, it decided on a system enabling switching to another PSK modulation system such as a quadrature PSK (QPSK) system since there is a tradeoff between efficiency of frequency utilization and tolerance to attenuation by rain and enabling achievement of a further higher service time rate. On the other hand, it also envisioned that a plurality of HDTV signals of different carriers would be multiplexed and transmitted by a single satellite repeater and considered as well transmission by a plurality of transport streams (TS) in order to improve the independence of Individual programs. Further, it called for multiplexing of transmission and multiplexing configuration control (TMCC) signals for control for transmission systems in areas other than MPEG control items, for example, the switching of the modulation systems and flexible configuration of a plurality of transport streams.
A TMCC signal contains TMCC information indicating a transport stream and modulation system for every slot data in a frame.
Below, an explanation will be made of the transmission line encoding system described in the report.
FIG. 1 is a view of the configuration of a broadcast satellite transmitter 1 employing the related transmission line encoding system.
As shown in FIG. 1, the broadcast satellite transmitter 1 has a Reed-Solomon encoder 2, a frame builder 3, an energy disperser 4, an interleaver 5, a convolution/trellis encoder 6, a TMCC signal generator 7, a Reed-Solomon encoder 8, an energy disperser 9, a modulator 10, and a burst signal generator 11.
The Reed-Solomon encoder 2 sequentially receives as its input, as shown in FIG. 2A, 188 bytes of Moving Picture Experts Group transport stream (MPEG-TS) packets S0 having one byte of an MPEG use synchronization word (47h) in a header, performs Reed-Solomon (204, 188) encoding on the MPEG-TS packets S0, and generates 204 bytes of slot data S2 shown in FIG. 2B comprised of the MPEG-TS packets S0 plus 16 bytes of parity data.
The frame builder 3, as shown in FIG. 2C, builds a frame FL1 by 48 slots SL1-1 to SL1-48 input from the Reed-Solomon encoder 2 and similarly builds frames FL2 to FL8. As shown In FIG. 3, it builds one super frame SFL by the eight frames FL1 to FL8.
Note that, in FIG. 3, a case where the header bytes of the slot data are replaced by a frame synchronization signal portion TAB2, a super frame synchronization signal TAB2, and a TMCC signal portion is shown, but the header bytes of the slot data in the super frame SFL built by the frame builder 3 become MPEG use synchronization words.
The energy disperser 4 performs energy dispersal processing for adding a pseudo random signal generated by for example xe2x80x9cX15+X14+1xe2x80x9d in order to avoid a succession of the same logic values except at the header bytes of the slot data (MPEG use synchronization words) in units of the super frames SFL input from the frame builder 3.
The interleaver 5 writes the super frame SFL subjected to the energy dispersal processing at the energy disperser 4 into a buffer memory and performs a read operation in a predetermined read direction except at the header byte of the slot data to thereby interleave the data.
The TMCC signal generator 7 uses the input TMCC information SI to generate, as shown in FIG. 4, 8 bytes of TMCC signals per frame and the 2 bytes of frame synchronization signal TAB1 and the super frame synchronization signal TAB2 added before and after them. As shown in FIG. 4, synchronization words W1 for frame synchronization are set in the frame synchronization signals TAB1 of the frames FL1 to FL8. The TMCC information is set in the TMCC signals of the frames FL1 to FL6. The parity data of the TMCC information to be added at the Reed-Solomon encoder 8 are set in the TMCC signals of the frames FL7 and FL8. A synchronization word W2 for super frame synchronization is set in the super frame synchronization signal TAB2 of the frame FL1. Synchronization words W3 for frame synchronization are set in the super frame synchronization signals TAB2 of the frames FL2 to FL8. Here, the synchronization word W3 is obtained by inverting all the bits of the synchronization word W2.
The Reed-Solomon encoder 8 performs Reed-Solomon (64, 48) encoding in units of the TMCC signals (TMCC information) of the frames FL1 to FL6 of the super frame SFL shown in FIG. 4 and sets the resultant parity data in the TMCC signals of the frames FL7 and FL8 shown in FIG. 4. The Reed-Solomon encoder 8 does not encode the frame synchronization signal TAB1 and the super frame synchronization signal TAB2.
The energy disperser 9 performs energy dispersal processing of the TMCC signals input from an external code error correctert 8. The energy dispersal processor 9 does not perform the energy dispersal processing for the frame synchronization signal TAB1 and the super frame synchronization signal TAB2 but outputs them as they are.
The convolution/trellis encoder 6 generates transmission signals by replacing the header bytes of the slot data of the super frame SFL input from the interleaver 5 by the frame synchronization signal TAB1, the TMCC signal, and the super frame synchronization signal TAB2 from the energy disperser 9, performs convolution encoding on the signals, among the related transmission signals, to be subjected to binary PSK (BPSK) or QPSK modulation at the modulator 10, and performs trellis encoding on the signals to be subjected to the 8PSK modulation at the modulator 10, and outputs the results thereof to the modulator 10.
The modulator 10 performs BPSK modulation on the convolution encoded frame synchronization signal TAB1, TMCC signal, and super frame synchronization signal TAB2 and sequentially transmits them, then transmits the main signals of the slot data modulated by the individual modulation systems and building the super frame SFL. Note that the modulation system of each slot data is designated by the TMCC information of the TMCC signal in the super frame two super frames before.
Further, the modulator 10 inserts and transmits a burst signal S11 generated at the burst signal generator 11 between the main signals of the modulated slot data in order to enable stable reception at the receiver by lowering a C/N characteristic.
Specifically, as shown in FIG. 5A, when looking at one frame""s worth of the transmission signal S10, the modulator 10 sequentially transmits one frame""s worth, that is, a total of 12 bytes, of the frame synchronization signal TAB1, TMCC signal, and the super frame synchronization signal TAB2 by using 192 symbols, then inserts and transmits 4 symbols of the BPSK modulated burst signal for every main signal of 203 symbols other than the 192 symbols of the TMCC signal based on the burst insertion control signal shown in FIG. 5B.
At this time, the 203 bytes of the slot data (main signal unit) other than the header bytes shown in FIGS. 5A and 5B are transmitted by 812 (203xc3x974) symbols.
Further, the modulation system of the main signal can be designated in units of slot data. When slot data of a plurality of modulation systems are transmitted by an identical carrier, the transmission is carried out in the order of the 203 bytes of the slot data modulated by the modulation system having the larger number of phases such as 8PSK, QPSK, and BPSK, that is, the slot data having the higher compression rates.
Note that, in practice, as the modulation system of the main signal, 8PSK is selected with the highest probability. In addition, 8PSK modulation is employed with a probability of close to 100% for the main signal of the slot data immediately after the super frame synchronization signal TAB2.
When the signal transmitted from the broadcast satellite transmitter 1 is received via the broadcast satellite at the broadcast satellite receiver, the broadcast satellite receiver first reproduces the carrier by using the TMCC signal and burst signal known to be subjected to the BPSK modulation. By reproducing the carrier in this way, the receiver can receive the signals stubbly even under conditions with a large noise level.
Next, the broadcast satellite receiver demodulates the received signals. At this time, it performs BPSK demodulation on the frame synchronization signal TAB1, TMCC signal, and super frame synchronization signal TAB2 since the modulation system is always BPSK.
Further, the corresponding TMCC signals for the main signals of the third and following super frames contained in the received signals are contained in the super frames two frames before as mentioned before, and the related TMCC signals have been already decoded. The receiver demodulates these signals based on the modulation system indicated by the related TMCC signals.
Summarizing the problems to be solved by the invention, as mentioned above, the broadcast satellite receiver has to first detect the TMCC signals in order to reproduce the carrier using the TMCC signal and the burst signal. Usually, there is the problem that the related TMCC signal cannot be detected unless the carrier is accurately reproduced.
For this reason, usually, the carrier is reproduced by regarding the entire received signals as a TMCC signal and burst signal known to have been modulated by BPSK in advance, the TMCC signal is detected in that process, and, after detecting the TMCC signal, the carrier reproduction circuit reproduces the carrier for only the portion of the TMCC signal and the burst signal under the control of the control circuit based on the detection timing of the TMCC signal.
The broadcast satellite receiver, however, requires a predetermined time from the reception of the TMCC signal to the detection of the TMCC signal. Therefore, at the time for outputting an instruction for stopping the carrier reproduction processing to the carrier reproduction circuit by the control circuit, the carrier reproduction circuit has already received as input signals other than the TMCC signal and the burst signal and has started the processing. Accordingly, there is a problem that noise enters the carrier reproduction loop, convergence is delayed, and the performance of the broadcast satellite receiver is lowered.
An object of the present invention is to provide a carrier reproduction circuit capable of reproducing a carrier of received signals at a high speed and high precision, a receiver using the related carrier reproduction circuit, and a loop filter circuit and an oscillator circuit used in the related carrier reproduction circuit.
According to a first aspect of the present invention, there is provided a carrier reproduction circuit of the present invention is a carrier reproduction circuit for reproducing a carrier of an input signal modulated to change in carrier according to the types of symbols by processing using a synchronization loop, comprising a differential detection circuit for detecting a difference between said input signal and a signal fed back in said synchronization loop to generate a first signal, a loop filter circuit for processing said first signal to generate a second signal by using a first integration loop containing a first delay circuit for giving n (n is a natural number), symbols"" worth of delay and inputting said first signal of m (m is a natural number) symbols before to said first integration loop in accordance with a switch signal, an oscillator circuit for feeling back an oscillation signal, which is produced by using said second signal by using a second integration loop containing a second delay circuit for giving n symbols"" worth of delay, toward said differential detection circuit, and switching said second integration loop to a state holding said second signal of m symbols before in accordance with said switch signal, and a signal generation circuit for generation a carrier reproduced signal by using said input signal and said oscillation signal.
The mode of operation of the carrier reproduction circuit of the present invention is as follows.
In the carrier reproduction circuit of the present invention, a synchronization loop (carrier reproduction loop) is configured by the differential detection circuit, loop filter circuit, and oscillator circuit.
The differential detection circuit detects the difference between the input signal and the signal fed back in the synchronization loop to generate the first signal.
Then, the loop filter circuit processes said first signal to generate the second signal by using the first integration loop containing the first delay circuit for giving n (n is a natural number) symbols"" worth of delay. At this time, when a switch operation is indicated by the switch signal, said first integration loop receives as input said first signal of m (m is a natural number) symbols before, and the first integration loop processes said first signal of m symbols before.
Then, the oscillator circuit processes said second signal by using the second integration loop containing the second delay circuit for giving n symbols"" worth of delay and feeds back the generated signal toward said differential detection circuit. At this time, when a switch operation is indicated by the switch signal, said second integration loop can be switched to the state holding said second signal of m symbols before.
The carrier reproduction circuit of the present invention, as mentioned above, can switch the first integration loop of the loop filter circuit and the second integration loop of the oscillator circuit to a state of m symbols before by the switch signal.
Further, in the carrier reproduction circuit of the present invention, preferably said input signal is a signal modulated to change in the phase of the carrier in accordance with the type of the symbol, said differential detection circuit generates said first signal indicating the difference in phases between said input signal and the signal fed back in said synchronization loop, and said carrier reproduction circuit further has a multiplier circuit for performing multiplication based on said signal fed back and said input signal to generate a carrier produced signal.
Further, in the carrier reproduction circuit of the present invention, preferably said loop filter circuit has a first adder circuit for adding said first signal and a third signal and outputting the result toward said first delay circuit, a third delay circuit for delaying the output of said first adder circuit by exactly m symbols, a selection circuit for selecting either of the output of said first delay circuit and the output of said third delay circuit in accordance with said switch signal and outputting the result as said third signal to said first adder circuit, and a second adder circuit for adding said first signal and the output of said first adder circuit to calculate said second signal.
Further, in the carrier reproduction circuit of the present invention, preferably said oscillator circuit has a first adder circuit for adding said first signal and a third signal and outputting the result toward said second delay circuit, an amplifier circuit for amplifying said first signal to mxc3x97s times when a single symbol can express s number of statuses, a second adder circuit for adding the output of said first adder circuit and the output of said amplifier circuit, a third delay circuit for delaying the output of said second adder circuit by exactly m symbols, and a selection circuit for selecting either of the output of said second delay circuit and the output of said third delay circuit in accordance with said switch signal and outputting the same as said third signal to said first adder circuit.
According to a second aspect of the present invention, there is provided a receiver for processing received signals containing a main signal modulated by a modulation system selected from among a plurality of modulation systems for changing the carrier in accordance with the type of the symbol and a modulation system indication signal indicating the modulation system of said main signal and modulated by a modulation system determined in advance, comprising a carrier reproduction circuit for processing said modulation system indication signal contained in said received signals to reproduce carriers by using a synchronization loop, a demodulation circuit for demodulating said carrier reproduced received signals by indicated demodulation systems, a signal detection circuit for detecting said modulation system indication signal contained in said demodulated received signals and outputting a detection signal indicating the related detection timing to said carrier reproduction circuit, and a demodulation system determination circuit for indicating the demodulation system corresponding to the modulation system indicated by said detected modulation system indication signal to said demodulation circuit, wherein said carrier reproduction circuit has a differential detection circuit for detecting a difference between said input signal and a signal fed back in said synchronization loop to generate a first signal, a loop filter circuit for processing said first signal to generate a second signal by using a first integration loop containing a first delay circuit for giving n (n is a natural number) symbols"" worth of delay and inputting said first signal of m (m is a natural number) symbols before to said first integration loop in accordance with a switch signal, an oscillator circuit for feeling back an oscillation signal, which is produced by using said second signal by using a second integration loop containing a second delay circuit for giving n symbols"" worth of delay, toward said differential detection circuit, and switching said second integration loop to a state holding said second signal of m symbols before in accordance with said switch signal, and a signal generation circuit for generation a carrier reproduced signal by using said input signal and said oscillation signal.
The mode of operation of the receiver of the present invention is as follows.
The carrier reproduction circuit reproduces the carriers by processing the modulation system indication signal contained in the received signals by using the synchronization loop.
Then, the demodulation circuit demodulates said carrier reproduced received signals by the designated demodulation system.
Then, the signal detection circuit detects said modulation system indication signal contained in said demodulated received signals and outputs the detection signal indicating the related detection timing to said carrier reproduction circuit.
Then, the demodulation system determination circuit instructs the demodulation system corresponding to the modulation system indicated by said detected modulation system indication signal to said demodulation circuit.
In the receiver of the present invention, the carrier reproduction circuit uses the detection signal output from the signal detection circuit to the carrier reproduction circuit as the switch signal of the carrier reproduction circuit and performs similar processing to that of the above carrier reproduction circuit.
Further, in the receiver of the present invention, preferably said received signal is a signal modulated for changing the phases of the carriers in accordance with the plurality of types of symbols, said differential detection signal is for generating said first signal indicating the difference in phase between said received signal and the signal fed back at said synchronization loop, and said carrier reproduction circuit further has a multiplier circuit for performing multiplication based on said signal fed back and said input signal to generate a carrier reproduced signal.
According to a third aspect of the present invention, there is provided a loop filter circuit comprising a first adder circuit for adding a first signal and a second signal, a first delay circuit for delaying the output of said first adder circuit by exactly n (n is a natural number) symbols, a second delay circuit for delaying the output of said first adder circuit by exactly m (m is a natural number) symbols, a selection circuit for selecting either of the output of said first delay circuit and the output of said second delay circuit in accordance with a switch signal and outputting the same as said second signal to said first adder circuit, and a second adder circuit for adding said first signal and the output of said first adder circuit to calculate said second signal.
Further, the loop filter circuit of the present invention is preferably used in a carrier reproduction circuit for reproducing the carrier of an input signal modulated to change in the phase of the carrier in accordance with the type of symbols by processing using a synchronization loop, and said first signal is a signal indicating the phase.
According to a fourth aspect of the present invention, there is provided an oscillator circuit used in a carrier reproduction circuit for reproducing a carrier of an input signal modulated to change in the phase of the carrier in accordance with the type of symbols by processing using a synchronization loop, comprising a first adder circuit for adding an input phase differential signal and phase signal to generate a carrier phase reproduced signal, a first delay circuit for delaying the output of said first adder circuit by exactly n (n is a natural number) symbols, an amplifier circuit for amplifying said phase differential signal to m (m is a natural number)xc3x97s times when a single symbol can express s number of statuses, a second adder circuit for adding the output of said first adder circuit and the output of said amplifier circuit, a second delay circuit for delaying the output of said second adder circuit by exactly m symbols, a selection circuit for selecting either of the output of said first delay circuit and the output of said second delay circuit in accordance with said switch signal and outputting the same as the phase signal to said first adder circuit, and a signal generation circuit for generating an oscillation signal having a phase indicated by said phase signal.